@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MF104 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/inf_ram_wrapper.vhd":85:7:85:21|Found compile point of type hard on View view:ctu_can_fd_rtl.inf_ram_wrapper_32_128_12_true_true(rtl) 
@N: MF104 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_core.vhd":100:7:100:14|Found compile point of type hard on View view:ctu_can_fd_rtl.can_core_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0(rtl) 
@N: MF104 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_top_level.vhd":103:7:103:19|Found compile point of type hard on View view:ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl) 
@N: MF105 |Performing bottom-up mapping of Top level view:ctu_can_fd_rtl.ctu_can_fd_libero_top(rtl) 
@N: MF106 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ctu_can_fd_libero_top.vhd":90:7:90:27|Mapping Top level view:ctu_can_fd_rtl.ctu_can_fd_libero_top(rtl) because 
