@W: MT530 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rst_sync.vhd":104:8:104:9|Found inferred clock can_top_level|clk_sys which controls 1501 sequential elements including rst_sync_inst.rff. This clock has no specified timing constraint which may adversely impact design performance. 
