@W: BN114 :|Removing instance CP_fanout_cell_ctu_can_fd_libero_top_rtl_inst (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1_acp(rtl)) because it does not drive other instances.
**** Begin Compile Point : can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 ****
@W: BN114 :|Removing instance CP_fanout_cell_inf_ram_wrapper_32_128_12_true_true_rtl_inst (in view: ctu_can_fd_rtl.inf_ram_wrapper_32_128_12_true_true_rtl_ilm(rtl)) because it does not drive other instances.
@W: FA239 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd":628:17:628:22|ROM rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/rx_buffer.vhd":628:17:628:22|ROM rx_buffer_inst.rwcnt_com[4:0] (in view: ctu_can_fd_rtl.can_top_level_128_8_true_true_true_true_true_true_true_63_true_1(rtl)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
**** End Compile Point : can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 ****
@W: BW110 :|Renaming port dff_arst_ctu_can_fd_rtl_ctu_can_fd_libero_top_rtl_0layer0_1 due to collision with Verilog/ System Verilog reserved word 
@W: BW110 :|Renaming port int_manager_12_8 due to collision with Verilog/ System Verilog reserved word 
@W: BW110 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/can_top_level.vhd":103:7:103:19|Renaming port can_top_level_128_8_true_true_true_true_true_true_true_63_true_1 due to collision with Verilog/ System Verilog reserved word 
@W: BW110 :"/DOKUMENTY/Projekty/ctu_can_fd/synthesis/Libero/parity_benchmark/ctu_can_fd_parity_benchmark_2/hdl/ctu_can_fd_libero_top.vhd":90:7:90:27|Renaming port ctu_can_fd_libero_top due to collision with Verilog/ System Verilog reserved word 
